Analog-to-digital converters are necessary to take the “real” analog world into the digital world. Real world responses are typically not always linear. Most often, the response signal may have to be manipulated before it can be utilized. A common manipulation technique for such manipulation is compression. Compression is an important type of signal processing and is used not only to increase the dynamic range but also linearize many exponential-like functions.
Compression increases the dynamic range of signals and if followed by decompression (e.g., companding) can raise the signal-to-noise (SNR) ratio. Compression can be performed in the analog domain using log amplifiers, as illustrated in FIG. 1, or in the digital domain as part of a digital signal processing (DSP) routine. In one exemplary approach, compressing A/D converters have been implemented using a successive-approximation technique with sampling rates of 4.5 Ms/second.
FIG. 1 shows a typical signal processing system 100 wherein A/D conversion can be performed in the analog domain using log amplifiers or in the digital domain as part of a digital signal processing (DSP) routine. The system 100 includes a sampler 102, an analog preprocessor 102, an analog-to-digital converter (ADC) 106, a digital signal processor (DSP) 108, and a communications/storage device 110.
The sampler 102 is configured to sample an analog input signal. The analog preprocessor 104 is configured to preprocess the sampled analog input signal. The ADC 106 is configured to convert an analog signal to a digital signal. The DSP 108 is configured to further process the digital signal. The communications/storage device 110 is configured to store and/or transmit the digital signal.
FIG. 2 is a schematic of a standard parallel Flash A/D converter 200. It is well known that flash A/D conversion is one of the most basic types of analog to digital conversion techniques. The Flash A/D converter 200 includes an input buffer 201, a plurality of comparators 202, a resistor ladder network 204, and an encoder 206. An input signal Vin is connected, via the input buffer 201, to the non-inverting inputs of 2N−1 parallel comparators. The inverting inputs of the respective comparators 202 are connected to an equal number of discrete reference voltages generated by the resistive ladder 204. Comparators 202 produce a logic “0” or “1” depending on whether the input voltage is lower or higher than the reference voltage. The comparators 202 produce an output of “thermometer” code (e.g., 0 . . . 01 . . . 1). The output of the comparators 202 are connected to the encoder 206 which produces a binary output depending upon where the “. . . 01 . . . ” transition is.
Various approaches exist for achieving compression in the signal processing chain, carried out as either analog compression or digital compression. Logarithmic amplifiers are commercially available which can perform the desired analog pre-processing. Logarithmic amplifiers are typically monolithic devices that have high power consumption (e.g., 25 mW) and DSP logic is intensive, leading to a large part count and excessive power dissipation. These devices are therefore not desirable for some applications, particularly silicon-on-chip (SoC) technologies. Besides logarithmic amplifiers, other analog pre-processors can achieve similar results, for example through the use of integrator and differentiator functionalities built from op-amp circuits. However, like most analog processors, these having high power consumption and are difficult to integrate on a chip.
Digital signal processing (DSP) can perform similar functions performed by analog processors. There are, however, problems associated with this approach. One of the goals of compression is to minimize the required resolution and consequently increase the available bandwidth of the A/D conversion process. In typical flash AND converters, since digital processing occurs after the conversion, such benefit of increasing the available bandwidth is eliminated. Further, DSP typically requires dedicated hardware, thus eliminating the goal of SoC integration. DSP also consumes high dynamic power and is mathematically intensive, leading to complex programming and lengthy application development cycles.
Most sensor applications require analog preprocessing followed by analog to digital conversion. Analog preprocessing tends to dissipate large amounts of power, uses a large die area, and can be difficult to execute in CMOS technology, for example, due to non-linearities resulting from process variations. Analog preprocessing typically involves amplification to rescale signals from low-level sensor or transimpedance amplifier outputs to be on the order of voltage rails for high resolution conversion at the risk of saturation. Signal-level compression is often desired to allow for a greater dynamic range. This processing is usually followed by ADC, for data transmission, storage or further processing. ADC is typically power-intensive and bandwidth limiting.
Accordingly, there is a need to overcome the above-identified problems.